1) Field of the Invention
The present invention relates, in general, to semiconductor device production, and more particularly, to gate contact and Source/Drain contact fabrication techniques for use in semiconductor production. The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making sub-quarter-micrometer gate electrodes by using a self-aligned mask to selectively form a low resistance gate contacts of titanium silicide or Cobalt silicide layer or other metal silicide films.
2) Description of the Prior Art
Advances in the semiconductor process technologies in recent years have dramatically decreased the device feature size and increased the circuit density and performance on integrated circuit chips. The field effect transistor (FET) is used extensively for Ultra Large Scale Integration (ULSI). These FETs are formed using polysilicon gate electrodes and self-aligned source/drain contact areas.
The conventional FETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single crystal semiconductor substrate. The gate electrode structure is used as a diffusion or implant barrier mask to form self-aligned source/drain areas in the substrate adjacent to the sides of the gate electrode. The distance from the source junction to drain junction under the gate electrode is defined as the channel length of the FET.
Advances in semiconductor technologies, such as high resolution photolithographic techniques and anisotropic plasma etching, to name a few, have reduced the minimum feature sizes on devices to less than a quarter-micrometer. For example, FETs having gate electrodes with widths less than 0.35 micrometers (um), and channel lengths that are less than the gate electrode width are currently used in the industry.
However, as this downscaling continues and the channel length is further reduced, the FET device experiences a number of undesirable electrical characteristics. One problem associated with these narrow gate electrodes is the high electrical sheet resistance which impairs the performance of the integrated circuit.
One method of circumventing this problem is to form on the gate electrode a metal silicide layer that substantially reduces the sheet resistance of the polysilicon gate electrode, and also the local electrical interconnecting lines made from the same polysilicon layer. A typical approach is to use a salicide process. In this process the polysilicon gate electrodes are patterned over the device areas on the substrate. Insulating sidewall spacers are formed on the sidewalls of the gate electrodes, and source/drain areas are implanted adjacent to the gate electrodes. Using the salicide process, a metal is deposited over the polysilicon gate electrodes and the self-aligned source/drain areas, and sintered to form a silicide layer on the polysilicon gates and silicide contacts in the source/drain areas. The unreacted metal on the insulating layer is selectively removed. Unfortunately, the formation of these salicide gate electrodes can result in undesirable effects, such as residual metal or silicide stringers extending over the narrow spacers causing electrical shorts between the gate electrodes and the source/drain areas.
A second problem results from forming titanium silicide on sub-quarter-micrometer FETs. The problem is that it is difficult to form low sheet resistance silicide on these sub-0.25-micrometer (um) gate lengths. One method to circumvent this problem is to use a cobalt or a nickel silicide to replace the titanium silicide. An alternative method to improve the sheet resistance is to amorphize the polysilicon layer by ion implantation prior to forming the titanium silicide. Still another problem arises if the polysilicon is amorphized by ion implantation using the salicide process. The implantation that occurs in the source/drain areas can result in crystalline damage, which can adversely affect the electrical characteristics of the device, and is not easily annealed out. Therefore it would be desirable to have a process that avoids this implant in the source/drain areas.
Performing salicidation on narrow poly lines in the deep-sub micron regime is getting extremely difficult especially the poly line width effect. New silicide materials such as COSi.sub.2 and NiSi.sub.2 have shown promising results but have yet to be implemented in the manufacturing as a viable process.
Basically, the diffusion coefficient of Co in Si is very high and as such, it is very hard to control the distribution of Co in the S/D region. However, Co has shown to be a very useful starting material for forming CoSi.sub.2 on the narrow poly lines due to its extremely small grains. NiSi.sub.2 is still at its infancy development since the major concern is its thermal stability at high temperature.
Therefore, there is still a strong need in the semiconductor industry for making sub-quarter-micrometer gate electrodes having lower sheet resistance using improved silicide techniques, and for controlling manufacturing costs by reducing the number of photoresist masking steps and other processing steps.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,731,239(Wong) shows a method of forming self aligned silicide contacts to the top of poly lines by etching back the oxide on top of the line. U.S. Pat. No. 4,912,061(Nasr) shows a disposable SiN spacer for a salicide process. However, these processes can be further improved.